SNST & Finger Vina Company
Internship position in SoC Design (20 Students in RTL Design, Synthesis, DFT, STA, Place & Route)
The SoC (System-on-Chip) Design Team is searching for a hands-on, team oriented, SoC
design and verification engineers with strong digital design, synthesis, place and route and
static timing expertise.
In this role you will be working as part of the team in all area of SoC design including RTL design, synthesis, physical design and timing closure of highly integrated, mixed-signal integrated circuits that implemented in latest technologies. You should have some knowledge
of RTL coding using Verilog/VHDL, logic synthesis, timing analysis, DFT, Place & Route and
physical design verification.
We offer professional training and support with competitive salary package and dynamic working environment.
The ideal candidates will meet some of the following requirements:
+ Familiar with Digital Logic Design and ASIC design flow
+ Knowledge of areas like Synthesis, DFT, Physical Design, Timing Analysis and Closure
+ Familiar with RTL languages such as Verilog/VHDL
+ Unix/Linux background desired
+ Can use English in communication and writing
+ Degree: Last year student majoring in Electronic Engineering or equivalent
+ Training: technical and non-technical skills from at latest 3 months.
+ Having lunch at office
Working place: SCS Building, Saigon High Tech Park, District 9, Ho Chi Minh City.
Interested candidates kindly send your application letter and CV via:
– Telephone: 028 7109 9401
Bộ môn Kỹ thuật Máy tính – Viễn thông
Khu C Khoa Điện – Điên tử
Trường Đại học SPKT TP.HCM
01 Võ Văn Ngân, Quận Thủ Đức
Thành Phố Hồ Chí Minh
Mon – Fri 7:00A.M. – 6:00P.M.